The present invention generally relates to the field of microelectromechanical systems and, more particularly, to a unit cell that facilitates the layout of at least a portion of such a system.
There are a number of microfabrication technologies that have been utilized for making microstructures (e.g., micromechanical devices, microelectromechanical devices) by what may be characterized as micromachining, including LIGA (Lithography, Galvonoforming, Abforming), SLIGA (sacrificial LIGA), bulk micromachining, surface micromachining, micro electrodischarge machining (EDM), laser micromachining, 3-D stereolithography, and other techniques. Bulk micromachining has been utilized for making relatively simple micromechanical structures. Bulk micromachining generally entails cutting or machining a bulk substrate using an appropriate etchant (e.g., using liquid crystal-plane selective etchants; using deep reactive ion etching techniques). Another micromachining technique that allows for the formation of significantly more complex microstructures is surface micromachining. Surface micromachining generally entails depositing alternate layers of structural material and sacrificial material using an appropriate substrate (e.g., a silicon wafer) which functions as the foundation for the resulting microstructure. Various patterning operations (collectively including masking, etching, and mask removal operations) may be executed on one or more of these layers before the next layer is deposited so as to define the desired microstructure. After the microstructure has been defined in this general manner, the various sacrificial layers are removed by exposing the microstructure and the various sacrificial layers to one or more etchants. This is commonly called xe2x80x9creleasingxe2x80x9d the microstructure from the substrate, typically to allow at least some degree of relative movement between the microstructure and the substrate.
It has been proposed to fabricate various types of optical switch configurations using various micromachining fabrication techniques. One of the issues regarding these types of optical switches is the number of mirrors that may be placed on a die. A die is commonly referred to as that area defined by one field of a stepper that is utilized to lay out the die. Reducing the size of the mirrors in order to realize the desired number of mirrors on a die may present various types of issues. For instance, there are of course practical limits as to how small the mirrors can be fabricated, which thereby limits the number of ports for the optical switch. Also, the optical requirements of the system using the mirrors may require mirrors larger than some minimum size. Therefore, it may not be possible to fabricate the optical switch with a certain number of ports using a single die. This presents a challenge regarding how to route electrical signals.
The present invention generally relates to a unit cell. This unit cell may be used to create a layout for at least part of a microelectromechanical system. Although this unit cell will contain at least a plurality of electrical lines, conductors, traces, or the like (hereafter xe2x80x9ctracesxe2x80x9d), various microstructure assemblies (e.g., one or more electrical load-based microstructures) may be included as part of the unit cell as well. Generally, the unit cell meets a number of predetermined boundary conditions such that once this unit cell is drawn or otherwise created, it may be simply copied, translated, and pasted an appropriate number of times to define at least part of a microelectromechanical system. This process may be collectively characterized as tiling the unit cell. In any case, a plurality of structurally identical unit cells will be placed in end-to-end relation in one or more rows as desired/required. Adjacent unit cells in each row will be electrically interconnected based upon the unit cell satisfying the predetermined boundary conditions.
A first aspect of the present invention is embodied by a chip that is formed using a plurality of unit cells. Each unit cell is structurally identical, and therefore only one unit cell need be described. The unit cell includes first and second sides. A plurality of these unit cells may be disposed in end-to-end relation to define a row that at least generally extends in a first direction. More specifically, the first side and second side of each adjacent pair of unit cells in a given row will be disposed up against each other such that the first and second sides of the unit cell will be spaced from each other in the first direction. In the event that a row of unit cells is characterized as being laterally extending (e.g., extending along/defining a width dimension for the chip), the first and second sides of the unit cell could then be characterized as being laterally spaced. The unit cell includes a plurality of first electrical traces that extend between its first and second sides. The unit cell also includes a plurality of second electrical traces. These second electrical traces extend from any of the first and second sides and terminate within the unit cell (i.e., at an interior location). Therefore, both ends of each first electrical trace are disposed on a perimeter of the unit cell. However, only one end of each second electrical trace is disposed on a perimeter of the unit cell.
There are a number of boundary conditions associated with the unit cell of the first aspect. For ease of description of these boundary conditions, a row of unit cells on the chip will be characterized as at least generally extending in a first dimension (e.g., a width dimension for the chip). A second dimension is perpendicular to this first dimension (e.g., a height dimension for the chip). The first and second dimensions may be such that they collectively define a plan view of the chip formed from the unit cells. The required boundary conditions for the unit cell are as follows: 1) each first electrical trace at the first side of the unit cell, and either a different first electrical trace at the second side of the unit cell or a second electrical trace at the second side of the unit cell, are disposed along a common reference line that is parallel with the first dimension; 2) each first electrical trace at the second side of the unit cell, and either a different first electrical trace at the first side of the unit cell or a second electrical trace at the first side of the unit cell, are disposed along a common reference line that is parallel with the first dimension; 3) each second electrical trace that is disposed on the first side of the unit cell and one first electrical trace on the second side of the unit cell are disposed along a common reference line that is parallel with the first dimension; and 4) each second electrical trace that is disposed on the second side of the unit cell and one first electrical trace on the first side of the unit cell are disposed along a common reference line is parallel with the first dimension.
Various refinements exist of the features noted in relation to the first aspect of the present invention. Further features may also be incorporated in the present invention as well. These refinements and additional features may exist individually or in any combination. The noted boundary conditions facilitate the electrical interconnection of adjacent unit cells in a row from which a chip may be formed. Any number of first and/or second electrical traces may exist within the unit cell and still satisfy the noted boundary conditions. However, in one embodiment, there is an even number of first electrical traces, an even number of second electrical traces, or both. One or more second electrical traces may extend from the first side of the unit cell, one or more second electrical traces may extend from the second side of the unit cell, or both and still satisfy the above-noted boundary conditions as well. In one embodiment, none of the traces in the unit cell cross over each other.
Additional boundary conditions may exist for the unit cell in relation to the first and second electrical traces. For instance, each of the first electrical traces at the first and second sides of the unit cell may be offset in a direction that is perpendicular or orthogonal to the first direction in which the noted row of unit cells at least generally extends. Each second electrical trace at its corresponding first or second side of the unit cell and where the particular second electrical trace terminates at its corresponding interior location within the unit cell may be offset in a direction that is perpendicular or orthogonal to the first direction in which the noted row of unit cells at least generally extends as well.
A spacing between the first and second sides of each unit cell associated with the first aspect may correspond with a single exposure field of photolithographic stepper. Stated another way, the spacing between the first and second sides of each unit cell may correspond with one dimension of a die (e.g., a die width). As used herein, a xe2x80x9cdiexe2x80x9d means an area encompassed by a single exposure field of a photolithographic stepper. Each unit cell may define at least a portion of a die. Another option is for each unit cell to define an entire die. In this case where the chip includes multiple unit cells/die in the noted row, the chip may further include a second row of a plurality of partial unit cells or partial die. Yet another option is for the chip to include multiple rows, each having a plurality of the noted unit cells disposed in end-to-end relation. A first group of rows may encompass at least part of a first die, and a second group of rows may encompass at least part of a second die. No single row of unit cells is in both the first and second group in this instance. In one embodiment, the first group of rows encompasses the entire first die, while the second group of rows encompasses only part of the second die.
The unit cell associated with the first aspect many include one or more electrical load-based microstructures disposed within the interior of the unit cell. Each electrical load-based microstructure could then be interconnected with a different, single second electrical trace. In the case where there are a plurality of electrical load-based microstructures in the unit cell, each of these microstructures may be of the same type or there may be at least two different types of such microstructures. In one embodiment, the noted electrical load-based microstructures are actuators of a mirror assembly that includes a mirror and an elevation structure interconnected with the mirror, such that at least one actuator may be interconnected with the elevation structure to move the corresponding mirror in a desired manner. The plurality of unit cells utilized by the chip may then define or be characterized as a mirror array.
In what may be characterized as a first embodiment, the first side of a first unit cell of the chip of the first aspect may define a first chip side, while the second side of a second unit cell of the chip may define a second chip side. The chip in this first embodiment may include at least one device region that is disposed between the first and second chip sides, a first off-chip contact region that is located between the first chip side and the device region that is closest to first chip side, and a second off-chip contact region that is located between the second chip side and the device region that is closest to the second chip side. At least one electrical load-based microstructure may be disposed in at least one of the device regions in the case of the first embodiment, and more typically at least one electrical load-based microstructure will be disposed in each device region in the case of the first embodiment. Each electrical load-based microstructure may be separately and independently addressed from at least one of the first and second off-chip contact regions in the first embodiment. The first and second off-chip contact regions in this first embodiment each may include a plurality of off-chip electrical contacts. Each off-chip electrical contact may be in the form of a pad for wire bonding, solder bump bonding, or the like. Each off-chip electrical contact may be associated with a different electrical path. This electrical path may be defined by only one second electrical trace, one second electrical trace and one or more first electrical traces, or a plurality of first electrical traces.
The chip of the first aspect may include first and second rows, each having a plurality of microstructure assemblies. An electrical trace bus may be located between these first and second rows of microstructure assemblies and at least the bus may be defined by the unit cells of the first aspect. That is, the noted plurality of first and second electrical traces collectively define the electrical trace bus. In one embodiment, the electrical trace bus is interconnected with at least some of the microstructure assemblies in one of the first and second rows, and none of the microstructure assemblies in the other of the first and second rows (e.g., the electrical trace bus services only one of the first and second rows, and not the other of the first and second rows). In another embodiment, the electrical trace bus is interconnected with at least some of the microstructure assemblies in both of the first and second rows (e.g., the electrical trace bus services both of the first and second rows). Each microstructure assembly may be a mirror assembly that includes a mirror, an elevation structure interconnected with the mirror, and at least one actuator interconnected with the elevation structure. A different second electrical trace would thereby xe2x80x9cpeel offxe2x80x9d from the noted electrical trace bus and progress to each of these actuators.
A plurality of rows of mirror assemblies of the above-noted type may be disposed on the chip. At least one second electrical trace may be interconnected with each actuator of each mirror assembly. These mirror assemblies may be disposed on the chip in a variety of arrangements. In one embodiment, a center of each mirror in a given row is disposed along a common reference line. In another embodiment, a center of each mirror in a given row may be alternately disposed on opposite sides of a central reference line. In either case, the mirrors in a given row may be equally spaced in relation to a direction in which the row at least generally extends. Preferably, the width of the chip is an integer multiple of the noted mirror spacing.
Each unit cell of the first aspect may include what may be characterized as a device region that is disposed inwardly of the first and second sides of the unit cell. A plurality of off-chip electrical contacts may be disposed between the device region and the first side of the unit cell, and a plurality of off-chip electrical contacts may be disposed between the device region and the second side of the unit cell. As such, when a plurality of unit cells are disposed in end-to-end relation, the chip will include at least one pair of interior regions that each have a plurality of off-chip electrical contacts. These particular xe2x80x9cinteriorxe2x80x9d off-chip electrical contacts will typically not used be used for providing a signal to or reading a signal from the chip. Instead, these xe2x80x9cinteriorxe2x80x9d off-chip electrical contacts may simply function as a passive electrode.
The plurality of first and second electrical traces associated with each unit cell may collectively define an electrical trace bus. At least some of the second electrical traces may be interconnected with an electrical load-based microstructure (e.g., an actuator of a mirror assembly of the above-noted type). In one embodiment a maximum number of electrical traces along any portion of the electrical trace bus is one-half of the number of electrical load-based microstructures that are interconnected with any second electrical trace of the noted electrical trace bus. The layout of the plurality of first and second electrical traces in the unit cell may also be such that the number of electrical traces in the electrical trace bus varies along the length of the electrical trace bus. In this regard, the noted electrical trace bus may include a plurality of first and second electrical trace bus segments, with a second electrical trace bus segment being disposed between adjacent pairs of first electrical trace bus segments. In one embodiment, the same number of electrical traces are included in each first electrical trace bus segment, the same number of electrical traces are included in each second electrical trace bus segment, and the numbers of electrical traces in the first and second electrical trace bus segments are different.